1. Field of the Invention
Example embodiments of the present invention relate generally to a memory device and method for operating the same, and more particularly to a memory device and method of performing memory operations on the memory device.
2. Description of the Related Art
Non-volatile memory devices may retain stored data even if power is not continuously provided. Flash memory devices may be examples of non-volatile memory devices. Examples of flash memory devices may include a floating-gate type memory device, in which a floating gate may be formed between dielectric layers for accumulating electric charges, and a charge-trap type memory device, in which a charge trapping layer may be formed between dielectric layers for accumulating electric charges by using the charge trapping layer as a storage node.
An example of the charge-trap type memory device may be a silicon-oxide-nitride-oxide-silicon (SONOS) memory device that uses a silicon nitride layer as the charge trapping layer. In a conventional SONOS memory device, a tunnel insulation layer, a charge trapping layer, and a blocking insulation layer may be stacked on a silicon substrate where a source region and a drain region may be formed, and a gate electrode may be formed on the blocking insulation layer. The tunnel insulation layer and the blocking insulation layer may be formed substantially of silicon oxide (SiO2), and the charge trapping layer may be formed substantially of silicon nitride (Si3N4).
If a silicon nitride layer is used for the charge trapping layer, an erasing speed (e.g., “clearing” data of the SONOS memory device, such as to a default logic level) under a negative voltage bias may be relatively low and a programming speed under a positive voltage bias may be relatively high, as shown in FIGS. 1A and 1B.
FIG. 1A illustrates flat band voltage shifts (V_FB[V]) with respect to programming time if positive voltage biases are applied to a conventional SONOS memory device. FIG. 1B illustrates flat band voltage shifts (V_FB[V] with respect to erasing time if negative voltage biases are applied to a conventional SONOS memory device.
In a NAND-type flash memory device, such as a SONOS memory device that employs Fowler-Nordheim (F-N) tunneling, a positive voltage bias may be applied to the memory device for programming in units of a “page” and a negative voltage bias may be applied to the memory device for erasing in units of a “block”.
However, if the trapping layer is formed of a material that responds relatively slowly to a positive voltage but relatively quickly or rapidly to a negative voltage, the above-described scheme using a positive voltage bias for programming in units of a page and a negative voltage bias for erasing in units of a block may be inefficient.